You can improve performance in magnitudes by being mindful of how you write your VHDL code. Many FPGAs have logic elements that can double as specialized shift register primitives. While any shift register is suitable for creating generic, smaller buffers, there are methods of efficiently creating larger ones. Read about how to create a ring buffer FIFO in block RAM to learn about such a solution that’s not a shift register. This article will only consider the shift register, even though there exist data structures that use fewer resources for larger FIFOs. To understand the basics of the shift register, I recommend viewing the VHDL tutorial about the std_logic_vector. Every time a new element enters the queue, it shifts the existing ones one place further away from the input. You can dramatically reduce the number of consumed resources by choosing the right shift register implementation for your needs and FPGA architecture.Ī shift register implements a FIFO of fixed length. There are many ways to create a shift register in VHDL, though not all of them are equal.
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